Phase locked loops are critical circuit elements used in various applications including clock generation and clock recovery. FIG. 1 shows the block diagram of a conventional PLL circuit that includes a crystal oscillator 1 for generating a low noise reference frequency clock signal (fref). The reference frequency clock signal fref is supplied to one input of a phase detector 3 having a second input that is supplied to the output (fout/N) of a divide-by-N circuit 8, where N is the frequency divider value. The output of the phase detector 3 supplies an up-count or a down-count signal to a charge pump circuit 4. The charge pump circuit 4 then supplies a current output to charge or discharge a filter network 5 whose output (in the form of a control voltage) is supplied to the input of a VCO 6, which produces an output clock signal fout having a frequency equal to (N*fref). The output clock signal fout is supplied to a divide-by-N network 8 to produce a feedback signal equal to fout/N which is supplied to the phase detector 3.
Another important aspect of a PLL characteristic is to have low-jitter at the output clocks. With reference to FIG. 1, two identified noise sources which may cause jitter in the output clock signal fout is noise nref 2 associated with the reference frequency fref and noise nvco 7 associated with the VCO 6. Typically, the noise nvco 7 is much greater than the noise nref 2 and is the leading cause of jitter at the PLL output. When the VCO noise dominates, [R. E. Best, “Phase Locked Loops”, second edition, McGraw Hill Publications, 1993] the output noise associated with the VCO (and hence, the output clock signal fout) can be reduced by increasing the PLL bandwidth ωBW.
At the start of the locking procedure, the VCO 6 starts oscillating with a start-up frequency, which is the free-running frequency of the VCO. This frequency changes with time under control of the feedback loop till the PLL becomes locked to the desired frequency. The time that a PLL takes to settle to its stable or locked state, starting from an unlocked and free-running state, is termed as the lock-time. A small lock-time is always a desirable feature. When the PLL is locked, the frequency difference between the reference clock (fref) and the feedback clock (fout/N) is zero.
A basic criteria to minimize the lock-time is to minimize the frequency difference between fref and (fout/N), so that a minimum time is required for the PLL to reduce the difference to zero. If the start-up frequency or the free-running frequency of the VCO 6 is designated as ffr, where ffr=fout at t=0, then the initial frequency difference seen by the PLL, which has to be reduced to zero, could be expressed as Δω=|fref−(ffr/N)|. As can be seen, Δω is a function of N. Therefore, if the VCO is always started with frequency ffr irrespective of the value N, then the frequency difference increases with N. This results in an increasing lock time, as one goes from a lower to a higher frequency divider value N. In the worst case the PLL may not get locked at all [R. E. Best, “Phase Locked Loops”, second edition, McGraw Hill Publications, 1993].
The lock time also depends on the frequency or phase step-response-time of the system, which is a function of the damping factor ζ and the natural frequency ωn of the PLL system. The transient, created by the frequency or phase step, is minimum if θ=0.7 and if the natural frequency ζn is large.
Thus, to achieve a constant and small lock-time, and to maintain an optimized settling and noise characteristic, an optimally designed PLL should keep the designed value of Δω and ωBW (and hence, ωn and ζ) independent of the division ratio N throughout its operation. However, in many applications, the division ratio N can not always be set to an optimum value because in those applications N is varied during the operation of the system. Common examples are clock-generator circuits used in microprocessors and communication systems, and PLL based frequency synthesizers. In these applications variation in N results in a non-optimal performance of the PLL and causes poor lock-time and settling behavior, apart from increasing the jitter in the VCO output.
There are no known techniques for making the PLL lock time independent of the frequency divider value or for minimizing the PLL lock time. U.S. Pat. No. 6,163,184 describes an improved phase locked loop (PLL) in which the bandwidth is independent of the frequency divider value. In this approach, the charge-pump current Icp or VCO gain KVCO, or loop-filter resistance R, can be programmed to vary as a function of N to render the bandwidth of the PLL independent of the divider ratio N. Implementation of this approach keeps the PLL bandwidth independent of the divider ratio N, but without maintaining and keeping the lock-time small as the count increases. The programmability is controlled by adjusting the current bias of the charge-pump or the VCO. However, this approach does not address the problem of minimizing or reducing the lock time.